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| SN54/74LS256 DUAL 4-BIT ADDRESSABLE LATCH The SN54/74LS256 is a Dual 4-Bit Addressable Latch with common control inputs; these include two Address inputs (A0, A1), an active LOW Enable input (E) and an active LOW Clear input (CL). Each latch has a Data input (D) and four outputs (Q0 - Q3). When the Enable (E) is HIGH and the Clear input (CL) is LOW, all outputs (Q0 - Q3) are LOW. Dual 4-channel demultiplexing occurs when the (CL) and E are both LOW. When CL is HIGH and E is LOW, the selected output (Q0 - Q3), determined by the Address inputs, follows D. When the E goes HIGH, the contents of the latch are stored. When operating in the addressable latch mode (E = LOW, CL = HIGH), changing more than one bit of the Address (A0, A1) could impose a transient wrong address. Therefore, this should be done only while in the memory mode (E = CL = HIGH). DUAL 4-BIT ADDRESSABLE LATCH LOW POWER SCHOTTKY * * * * * * Serial-to-Parallel Capability Output From Each Storage Bit Available Random (Addressable) Data Entry Easily Expandable Active Low Common Clear Input Clamp Diodes Limit High Speed Termination Effects J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 CL 15 E 14 Db 13 Q3b 12 Q2b 11 Q1b 10 Q0b 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC 1 A0 2 A1 3 Da 4 Q0a 5 Q1a 6 Q2a 7 Q3a 8 GND PIN NAMES LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.5 U.L. 0.25 U.L. 5 (2.5) U.L. 3 LOGIC SYMBOL 2 1 15 14 13 A0, A1 Da, Db E CL Q0a - Q3a, Q0b - Q3b Address Inputs Data Inputs Enable Input (Active LOW) Clear Input (Active LOW) Parallel Latch Outputs (Note b) 0.5 U.L. 0.5 U.L. 1.0 U.L. 0.5 U.L. 10 U.L. Da E NOTES: a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. A0 A1 CL A0 A1 CL E Db Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b 4 5 6 7 VCC = PIN 16 GND = PIN 8 9 10 11 12 FAST AND LS TTL DATA 5-1 SN54/74LS256 LOGIC DIAGRAM E 14 3 Da 1 A0 2 A1 15 CL 13 Db 4 5 6 7 9 10 11 12 Q0a VCC = PIN 16 GND = PIN 8 = PIN NUMBERS Q1a Q2a Q3a Q0b Q1b Q2b Q3b TRUTH TABLE CL L L L L L L L L L H H H H H H H H H E H L L L L L L L L H L L L L L L L L D X L H L H L H L H X L H L H L H L H A0 X L L H H L L H H X L L H H L L H H A1 X L L L L H H H H X L L L L H H H H Q0 L L H L L L L L L QN-1 L H QN-1 QN-1 QN-1 QN-1 QN-1 QN-1 Q1 L L L L H L L L L QN-1 QN-1 QN-1 L H QN-1 QN-1 QN-1 QN-1 Q2 L L L L L L H L L QN-1 QN-1 QN-1 QN-1 QN-1 L H QN-1 QN-1 Q3 L L L L L L L L H QN-1 QN-1 QN-1 QN-1 QN-1 QN-1 QN-1 L H MODE Clear Demultiplex Memory Addressable Latch H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial MODE SELECTION E L H L H CL H H L L MODE Addressable Latch Memory Dual 4-Channel Demultiplexer Clear FAST AND LS TTL DATA 5-2 SN54/74LS256 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 0.4 4.0 8.0 Unit V C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol S bl VIH VIL VIK VOH Parameter P Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage Output HIGH Voltage 54, 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current Others E Input Others E Input IIL IOS ICC Input LOW Current Others E Input Short Circuit Current (Note 1) Power Supply Current - 20 0.35 0.5 20 40 0.1 0.2 - 0.4 - 0.8 - 100 30 V A 2.4 - 0.65 3.5 0.25 0.4 0.8 - 1.5 V V V Min 2.0 0.7 V Typ Max Unit Ui V Test C di i T Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for p g All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V IIH mA VCC = MAX, VIN = 7.0 V mA mA mA VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25C) Limits Symbol S bl tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter P Turn-Off Delay, Enable to Output Turn-On Delay, Enable to Output Turn-Off Delay, Data to Output Turn-On Delay, Data to Output Turn-Off Delay, Address to Output Turn-On Delay, Address to Output Turn-On Delay, Clear to Output Min Typ 20 16 20 13 20 14 12 Max 27 24 30 20 30 24 23 Unit Ui ns ns ns ns ns ns ns Figure 1 Figure 2 Figure 3 Figure 5 Test C di i T Conditions VCC = 5.0 V, 50V CL = 15 pF FAST AND LS TTL DATA 5-3 SN54/74LS256 AC SET-UP REQUIREMENTS (TA = 25C) Limits Symbol S bl ts ts th th tW Parameter P Data Setup Time Address Setup Time Data Hold Time Address Hold Time Enable Pulse Width Min 20 0 0 15 15 Typ Max Unit Ui ns Figures 4 & 6 ns ns ns ns Figure 4 Figure 6 Figure 1 VCC = 5.0 V 50 Test C di i T Conditions AC WAVEFORMS D D tpw E tPHL Q OTHER CONDITIONS: CL = H, A = STABLE tPLH 1.3 V OTHER CONDITIONS: E = L, CL = H, A = STABLE tpw 1.3 V Q 1.3 V tPHL 1.3 V 1.3 V tPLH 1.3 V Figure 2. Turn-on and Turn-off Delays, Data to Output Figure 1. Turn-on and Turn-off Delays, Enable To Output and Enable Pulse Width A1 1.3 V 1.3 V D ts(H) th(H) ts(L) th(L) 1.3 V A1 Q1 1.3 V tPHL 1.3 V OTHER CONDITIONS: E = L, CL = L, D = H 1.3 V tPLH 1.3 V E Q Q=D Q=D OTHER CONDITIONS: C = H, A = STABLE Figure 3. Turn-on and Turn-off Delays, Address to Output Figure 4. Setup and Hold Time, Data to Enable C 1.3 V tPHL 1.3 V A ts E 1.3 V STABLE ADDRESS th 1.3 V Q OTHER CONDITIONS: E = H OTHER CONDITIONS: CL = H Figure 5. Turn-on Delay, Clear to Output Figure 6. Setup Time, Address to Enable (See Notes 1 and 2) NOTES: 1. The Address to Enable Setup Time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is addressed and the other latches are not affected. 2. The shaded areas indicate when the inputs are permitted to change for predictable output performance. FAST AND LS TTL DATA 5-4 |
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